VERILOG DIGITAL SYSTEM DESIGN RT LEVEL SYNTHESIS, TESTBENCH AND VERIFICATION (Record no. 53345)

MARC details
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9780070252219
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name "NAVABI, ZAINALABEDIN."
-- 1534
245 #0 - TITLE STATEMENT
Title VERILOG DIGITAL SYSTEM DESIGN RT LEVEL SYNTHESIS, TESTBENCH AND VERIFICATION
250 ## - EDITION STATEMENT
Edition statement 2
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Name of publisher, distributor, etc. TMH
365 ## - PRICE
Price 650
999 ## -
-- 53345
-- 53345
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Date acquired Total Checkouts Full call number Barcode Date last seen Price effective from Koha item type Date last checked out
    Dewey Decimal Classification     IET Lucknow Central Library IET Lucknow Central Library 17/09/2019   621.395 NAV 32759 17/09/2019 17/09/2019 Books  
    Dewey Decimal Classification     IET Lucknow Central Library IET Lucknow Central Library 17/09/2019 1 621.395 NAV 32760 13/11/2021 17/09/2019 Books 28/10/2021
    Dewey Decimal Classification     IET Lucknow Central Library IET Lucknow Central Library 17/09/2019   621.395 NAV 32761 17/09/2019 17/09/2019 Books  
    Dewey Decimal Classification     IET Lucknow Central Library IET Lucknow Central Library 17/09/2019 1 621.395 NAV 32762 05/05/2022 17/09/2019 Books 25/04/2022
    Dewey Decimal Classification     IET Lucknow Central Library IET Lucknow Central Library 17/09/2019   621.395 NAV 32763 17/09/2019 17/09/2019 Books  
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